ALATTIS Prototype Project
Request for White Papers
SOLUTIONS OVERVIEW INFORMATION
PROJECT OPPORTUNITY TITLE: Accelerated, Large-Area, 10-kV Thick-Epitaxial Insulated-Gate Bipolar Transistors (ALATTIS) Prototype Project
PROJECT SPONSOR: United States Army Development Command (DEVCOM), Army Research Lab (ARL)
ANNOUNCEMENT TYPE: Request for White Papers (RWP)
PROJECT OPPORTUNITY NUMBER: APEX-RWP-005-ALATTIS
IMPORTANT DATES [All times listed herein are Eastern Time (ET)]
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DESCRIPTION OF THE OPPPORTUNITY
The United States Army Development Command (DEVCOM), Army Research Lab (ARL) seeks solutions for a prototype effort to develop, execute, and validate a novel and currently unavailable domestic manufacturing process for ultra-high-voltage (≥10-kV) silicon carbide (SiC) power semiconductor devices. The Accelerated, Large-Area, 10-kV Thick-Epitaxial Insulated-Gate Bipolar Transistors (ALATTIS) prototype project will focus on iterative design, fabrication, and testing to demonstrate the technical feasibility, manufacturability, and scalability of a repeatable production process to repeatedly manufacture large-area, high-current SiC Insulated-Gate Bipolar Transistors (IGBTs) and associated diodes. It is expected that a least 1,100 devices will be manufactured overall as a product of the repetitive testing and development processes. The devices will be delivered to the Government and must meet key performance thresholds for Government testing and evaluation, supporting mission critical platforms used by the Armed Forces. The primary deliverable will be the successful demonstration of the prototype process reflecting a robust, manufacturable, and high-quality production capability of large area, high-current, devices with voltage ratings ≥10kV. The ALATTIS prototype project is UNCLASSIFIED.
AWARD AUTHORITY: 10 U.S.C. § 4022
The ALATTIS prototype project will develop, execute, and validate a novel domestic manufacturing process for ultra-high-voltage (≥10 kV) silicon SiC power semiconductor devices through iterative design, fabrication, and testing. Devices produced under this effort will serve as Government test articles to validate process feasibility, manufacturability, and scalability, with the primary deliverable being the demonstrated and repeatable fabrication process rather than a production system.
POINTS OF CONTACT
APEx Consortium Manager
Joint Experimentation and Technology Accelerator
Subject Line: APEX-RWP-005-ALATTIS
RWP DOWNLOAD INSTRUCTIONS
To view and download the entire ALATTIS prototype project RWP to include the associated attachments, click on the button below. As a reminder, to access the documents you must be a paid member in good standing in the Advanced Prototyping and Experimentation (APEx) Consortium and be a member in good standing in the Tech Accelerator Community. If you are not a paid member in good stadning you can start and complete the application process at www.techaccelertor.us/membership.
SOLUTIONS SUBMISSION INSTRUCTIONS
Submit your solution(s) for this opportunity by clicking the button below. As a remider, you must be a paid member in good standing in the Advanced Prototyping and Experimentation (APEx) Consortium and be a member in good standing in the Tech Accelerator Community. to submit solution(s) to this opportunity.
Submit questions or feedback regarding this opportunty to info@techacclerator.us.